1. Field of the Invention
This invention relates to hardware emulation systems using field-programmable gate arrays (FPGA's), and more particularly to an emulator using a disposable wire-wrap board for interconnecting FPGA's.
2. Description of the Related Art
Digital circuits and systems have become ever more complex and difficult to debug. Designers often use software-based simulators to validate or test their designs before manufacturing silicon prototypes, but the extent of the testing is limited by the relatively slow speed of the software simulator. Although software simulators are relatively inexpensive, they are slow since they simulate the logic gates of the design using routines of instructions such as single-bit write and test instructions. Logical states of nodes may have to be stored in a main memory or even on a hard disk, further slowing simulation. Complex designs such as microprocessors often require millions of test vectors which can occupy days or weeks of software simulation time.
Higher-speed hardware-based emulators have emerged to accelerate design validation, allowing millions of test vectors to be executed before a silicon prototype is manufactured. Actual application programs for the target design can be executed on the hardware-based emulator. Hardware-based emulators are commercially available from companies such as IKOS Systems of Cupertino, Calif., Aptix Corp. of San Jose, Calif., and Quickturn Systems of Mountain View, Calif.
These hardware-based emulators emulate the design's logic gates using real hardware logic gates in a field-programmable gate array (FPGA) rather than with logical instructions executed on a microprocessor. FPGA's are commercially available from such firms as Altera of San Jose, Calif., Xilinx of San Jose, Calif., and Actel of Sunnyvale, Calif.
HARDWARE EMULATORS USE FPGA CHIPS FOR RE-PROGRAMMABLE INTERCONNECTIONS
Hardware emulators also use FPGA's for interconnection as well as for the logic gates being emulated. For example, U.S. Pat. No. 5,352,123 by Sample et al. and assigned to Quickturn Systems of Mountain View, Calif. shows a multi-board emulator with FPGA chips for both logic emulation and for interconnecting other FPGA's.
FIG. 1 is a diagram of a prior-art hardware-based emulator using FPGA chips for interconnection. Emulation board 16 contains several FPGA chips 10 which are programmed to contain some of the logical gates in a design being emulated. These logical gates are connected together with each of the FPGA chips 10 using internal interconnect, but some gates must be connected to gates in other FPGA chips. Thus other FPGA chips are used as switch chips 12. Switch chips 12 are simply used for interconnecting FPGA chips 10 to each other and to other boards. The logic gates within switch chips 10 are generally not used since switch chips 10 simply function as a cross-bar switch.
Larger designs cannot be fit on a single emulation board, so connection must be made to other emulation boards. Switching board 18 also contains FPGA programmed as cross-bar switches 14. These FPGA cross-bar switches form programmable connections from switch chips 12 on emulation board 16 to other emulation boards. Thus a large design can be emulated by connecting many emulation boards to switch board 18. External inputs and outputs (I/O) also connect to cross-bar switches 14.
Such hardware emulators can be re-programmed to emulate other designs, and thus can be re-used over and over again. However, such emulators are expensive and can cost hundreds of thousands or millions of dollars. Often more FPGA's are needed for the interconnection than for the logic gates being emulated. Larger emulators in particular can require many cross-bar switch FPGA's when any FPGA can be connected to any other FPGA. Thus many of the FPGA's are used simply for interconnect. Indeed, more FPGA's are used for interconnection than for logic-gate emulation on some systems, requiring additional circuit-board area for the interconnection FPGA's.
The interconnection architectures in U.S. Pat. Nos. 5,352,123 and 5,414,638 provide interconnection from any pin of a user component to any pin of another user component. A common disadvantage of these architectures is the use of many interconnection chips to make these connections. Using interconnection chips increases timing delays, chip counts, and board space, resulting in a slower, larger, complicated and expensive system.
CUSTOM PCB'S WITH FPGA'S
Designs in netlist form can be read, synthesized, partitioned and loaded into multiple FPGA's using a FPGA compiler such as Altera's MAXPLUS II. A report file from the compiler specifies the interconnection between FPGA chips. The system can then be prototyped by programming the FPGA's and creating a custom PCB with the interconnection specified by the report file.
Unfortunately, interconnection using custom PCB's must go through layout, component placement, routing of nets, assembly, and testing. Designing and manufacturing custom PCB's can take weeks, and each new design must have a new custom PCB made. More extensive changes to a design often require a new PCB layout.
What is desired is a hardware-based emulator using FPGA's for logic-gate emulation but not using FPGA's for interconnection. It is desired to reduce cost and timing delay by eliminating interconnection FPGA's while still using FPGA's for logic emulation. It is desired to segregate the relatively expensive FPGA's from the less expensive interconnect. Fast prototyping is desired for the interconnect. PCB interconnect is desired to be replaced with a more rapidly constructed interconnection technology.